1. Field of the Invention
The invention relates to bus switching techniques. Specifically, the invention relates to certain improvements over the solution disclosed in U.S. Pat. No. 6,933,863, the entire disclosure of which is incorporated herein by reference.
2. Description of the Related Art
The scenario of new sub-micrometric technologies (DSM) allows integration of increasingly more complex devices in increasingly smaller silicon wafers, while also effectively controlling power consumption and speed performance of the related systems. Current forecasts indicate the possibility of integrating increasingly more complex systems, while being able to control power consumption at both the technological and system levels. However, while future systems are expected to have very small dissipation levels, energy consumption by interconnection units is not expected to follow that trend. This applies particularly to off-chip electrical buses, with the ensuing dissipation level of the units that drive the associated pads and the power consumption process related to the process of charging and discharging the parasitic capacitances associated therewith.
In fact, a generic node i, fed with a voltage Vdd and having associated a parasitic capacitance Ci, dissipates at an operating frequency f a dynamic power Pi given by:
                              P          i                =                              1            2                    ·                      C            i                    ·                      V            dd            2                    ·          f          ·          α                                    (        1        )            where α (alpha) is the so-called switching activity, namely the percentage of 1→0 and 0→1 transitions that occur in a time unit. It will be appreciated that the dependency on the voltage Vdd follows a quadratic law, while the dependency on the other parameters is linear.
Prior art techniques for reducing the dissipated power Pi typically rely on reducing the voltage Vdd (which may turn out not be feasible due to the need of ensuring signal integrity against disturbances), lowering of the operating frequency f (which inevitably impacts on performance), or signal encoding to reduce inasmuch as possible the parameter α. In fact, bus-encoding techniques act on switching activity, namely the parameter α, without affecting system performance or its capacitance to reject disturbances affecting the useful signal.
Bus encoding is convenient if the additional consumption related to the presence of the encoding/decoding systems is lower than the energy savings achieved on the bus. In general terms, encoding an address bus is simpler than encoding a data bus.
This is because of the spatial and temporal (time) locality principle that governs the generation of addresses in a CPU.
Simply stated:
temporal or time locality means that, if a CPU uses a certain resource at a time t, then a substantial likelihood exists that it will be using that resource at a slightly later time;
spatial locality means that a CPU uses a certain location at a time t, then a substantial likelihood exists that at a slightly later time that CPU will be using a location nearby.
These considerations are exploited, e.g., in “cache” memories, which strongly reduce the times of access to an external memory by storing the locations that are used more frequently.
Bus encoding techniques tend to become less effective as the bus size, and consequently the transmission rate increase. To counter this, one of the simplest bus encoding techniques is the so-called “bus-invert” technique. This is based on the concept of estimating the switching activity associated with the transmission of a given set of data over the bus and complementing (i.e., chenging 1→0 and 0→1) the set of data transmitted if the estimated switching activity exceeds 50%.
In particular, in the presence of identical line capacitances, the parameter α (alpha) is measured by counting the number of logical “1s” in the transition between B(t−1) and B(t), that is in the transition between two subsequent states of the bus output.
In mathematical terms, if the bus has N lines (“wires”):
                              B          ⁡                      (            t            )                          =                  {                                                                      b                  ⁡                                      (                    t                    )                                                                                                                    H                    ⁡                                          [                                                                        b                          ⁡                                                      (                            t                            )                                                                          ⊕                                                  B                          ⁡                                                      (                                                          t                              -                              1                                                        )                                                                                              ]                                                        <                                      N                    /                    2                                                                                                                                            b                    _                                    ⁡                                      (                    t                    )                                                                                                                    H                    ⁡                                          [                                                                        b                          ⁡                                                      (                            t                            )                                                                          ⊕                                                  B                          ⁡                                                      (                                                          t                              -                              1                                                        )                                                                                              ]                                                        ⁢                                      >                    _                                    ⁢                                      N                    /                    2                                                                                                          (        2        )            where b(t) represents the bus input at time t (i.e., the string of bits to be transmitted in parallel over the bus at time t) and ⊕ denotes the Exclusive-OR (X-OR) logical operator
The parameter α (alpha) is computed by using the Hamming operator (H), that is by counting the number of “1s” in the Exclusive-OR above.
Such an approach is no longer accurate if the capacitances in the bus are not identical. In that case, the dynamic switching power P, that is the power related to loading/unloading the bus self capacitances, becomes (for a bus of N identical lines):
                    P        =                              ∑                          i              =              1                        N                    ⁢                                          ⁢                                    1              2                        ·                          C              i                        ·            f            ·                          V              dd              2                        ·                          α              i                                                          (        3        )            
That formula includes constant factors (namely f, Vdd, ½=0,5). The parameter αi can be expressed as:
                              α          i                =                              lim                          T              ->              ∞                                ⁢                                                    n                i                            ⁡                              (                T                )                                      T                                              (        4        )            where N is the number of the lines in the bus, T is the time between two subsequent states in the bus (i.e., the time between two subsequent transmissions of data on the bus and ni(T) represents the total transitions (0→1 and 1→0) measured in the time interval [0,T] corresponding to the i-th bus line.
By purging the effects of the constants f, Vdd, N and 0.5, the “normalized” power therefore becomes, in the case of switching only (self capacitance activity):
                    p        =                              ∑                          i              =              1                        N                    ⁢                                          ⁢                                    C              i              s                        ·                          n              i                                                          (        5        )            
The quantity CS (S=self capacitance) takes into account (notonally for each bus line, thus the suffix i) the bus asymmetry, while the ni's can assume values equal to 0 or 1. The formula thus provides a value proportional to the energy dissipated for each cycle T.
As indicated, Bus Invert techniques are known in the art: see, e.g., K. W. Kim, K. Baek, N. Shanbag, C. L. Liu and S. Kang “Coupling Driven Signal Encoding Scheme For Low-Power Interface Design” in ACM/IEEE International Conference on CAD. November 2000, where a so-called Coupled Bus Invert (CBI) technique is known. Bus switching techniques, essentially aiming at reducing switching activity in large electrical buses are disclosed, e.g., in:
M. Olivieri, F. Pappalardo and G. Visalli “Bus-Switch Coding, For Reducing Power Dissipation In Off-Chip Buses” in IEEE Transaction on Very Large Scale integration Systems Volume 12 No. 12 Dec. 2004; or
U.S. Pat. No. 6,933,863 issued to G. Visalli and F. Pappalardo.
Specifically, U.S. Pat. No. 6,933,863 discloses a procedure that, from the logical point of view, is an iterative procedure. A large size bus is partitioned into a plurality of smaller identical clusters, so that the string of bits to be transmitted over the bus is similarly partitioned into a corresponding plurality of clusters of bits. Each cluster is re-ordered by resorting to an exchange sequence (reordering pattern) that admits only one inverse pattern for the recovering upon reception the data transmitted. Each cluster as re-ordered is subjected to a further encoding function, which leads to a further increase in performance. The encoder performs trials, evaluating that function by considering all the possible re-ordering patterns, and selecting the one that implies the minimum electrical activity (metric of the encoder) of the whole bus. The number of iterations is a function of the cluster depth based on a factorial law: a cluster of 4-lines admits 4!=24 possible sequences of re-ordering.
Crosstalk is another source of energy dissipation, which prevails in on-chip buses. In short, simultaneous switching on two adjacent bus lines connected by a parasitic capacitance leads to a disturbance overvoltage applied on a “victim” line plus power dissipated due to the change of polarity on the line.
FIG. 1 is a schematic representation of three adjacent bus lines including a “victim” line K, having two adjacent lines K−1 and K+1 likely to act as “attacker” lines with associated disturbance generators G1 and G2. CS and CL are representative of the “line” (self) and “crosstalk” capacitances, respectively. In order to properly take into account crosstalk, one must be able to evaluate the effects thereof with regard to the various possible logical states of both attacker and victim lines.
In fact Kim et al., cited previously, have already suggested a variation of the bus-invert technique somewhat intended to take into account crosstalk. That approach is essentially a coupling driver bus-invert (CBI) technique based on the hypothesis/assumption that the capacitances CS and CL are equal. This is inevitably a strong limitation and the effectiveness of the technique is thus limited to those situations that come sufficiently close to that assumption.